China’s chip manufacturing breakthrough: new GAA transistors open the way to a 3nm process, but face production challenges

Researchers from the Chinese Academy of Sciences (CAS) have made significant progress in developing gate-all-around (GAA) transistors, which show potential to deliver performance comparable to an advanced 3-nanometer process. This step could bring China closer to overcoming technological barriers in semiconductor manufacturing, allowing it to use existing legacy DUV lithography equipment to reach new standards. However, despite this scientific success, real-world scaling of production faces substantial obstacles related to the middle and back-end stages of the manufacturing process.

GAA technology: a new era in current control

Transistors, the foundation of all modern electronics, function as microscopic switches that control the flow of electric current. In CAS’s new developments, a GAA architecture has been used that differs fundamentally from the previous FinFET standard. If FinFET transistors have a vertical structure resembling fins, GAA transistors surround the electrical signal from all sides. This provides much more precise control over current, minimizing leakage and improving efficiency.

CAS specialists report impressive figures for their new transistors: the on/off ratio exceeds 500,000. This means the difference between current in the on and off states is enormous, indicating near-perfect control and, as a result, lower power consumption and higher speed.

DUV lithography and the challenge of the 3nm process

One of the key aspects of CAS’s development is the ability to manufacture these devices using DUV lithography systems. Although this technology is considered outdated for the most advanced process nodes, it has a major advantage in being widely available and less expensive than EUV lithography, which is used to produce the most advanced chips. Traditionally, the wavelength of light used in DUV lithography is insufficient to achieve the precision required for a 3nm process.

However, CAS researchers likely applied a combination of techniques such as multi-pattern etching to reduce layer thickness and immersion DUV lithography using ultra-pure water. These methods improve laser resolution, which in turn makes it possible to achieve parameters close to the 3nm standard, previously available only with EUV technology. Successful implementation of GAA transistors makes it possible to significantly reduce layout density while maintaining high performance that previously required the denser FinFET architecture.

Manufacturing limitations: MEOL and BEOL as the “bottleneck”

Despite significant progress in creating the transistors themselves (the Front-End-Of-The-Line, FEOL stage), the real challenge for Chinese manufacturers, including SMIC, lies in the subsequent production stages: Middle-End-Of-The-Line (MEOL) and Back-End-Of-The-Line (BEOL).

MEOL is responsible for creating the metal interconnects that link each transistor to the overall circuit. This process requires etching extremely precise trenches, which are then filled with metal. BEOL covers all outer layers of metal wiring that connect the chip’s components. Particularly difficult is producing the lowest metal layer, M0, which is the thinnest and closest to the transistors.

According to experts, these stages represent the biggest problem. Advanced GAA transistors, while improving efficiency at the individual component level, do little to simplify the complex MEOL and BEOL processes. The spacing between transistor gates, which is determined by MEOL capabilities, remains a critical factor.

Outlook and real achievements

Despite these manufacturing constraints, SMIC engineers have found a way to increase layout density. Reducing the fin pitch in the GAA architecture makes it possible to lower the height of logic cells. This, in turn, opens the possibility of moving from a 5-track to a 4-track M0 layer configuration.

Thanks to these optimizations, SMIC can begin using “G57H198” or “G54H198” logic cells. These cells have a density of 137.8 MTr/mm², approaching the figures of a 5nm process used by leading global manufacturers such as TSMC. Thus, even with the complex processes involved in forming the middle and lower layers of metal interconnects, SMIC could potentially reach performance levels equivalent to 5nm technologies. This is a major leap for China’s industry, helping to narrow the gap with global leaders while using its own manufacturing capabilities. However, achieving a true 3nm process, which requires access to EUV lithography, remains a long-term and difficult task for China.